unisonic technologies co., ltd UC3800 preliminary linear integrated circuit www.unisonic.com.tw 1 of 10 copyright ? 2015 unisonic technologies co., ltd qw-r103-083.a low cost power-saving mode pwm controller for flyback converters ? description the utc UC3800 is a high performance current mode pwm controller ideally suited for low standby power. high voltage startup is implemented in utc UC3800 , which features with short startup time and no standby current. at no l oad condition, the ic operates in power-saving mode for lower standby power, decreasing frequency for higher conversion efficiency at light load condition. the internal slope compensation improves system stability at high pwm duty cycle output. leading-edge blanking on current sense input removes the signal glitch, which offering minimal external component count in the design. excellent emi performance is achieved with utc proprietary frequency hopping technique (zl201020615247.1) together with soft driver control. audio noise is eliminated due to switch frequency more than 20khz during operation. the utc UC3800 has such applications as: battery charger, power adaptor, set-top box power supplies, ink jet printers, open-frame smps. ? features sop-8 * utc proprietary frequency hopping technology for improved emi performance. * power-saving mode for high light-load and standby efficiency * soft start * dynamic peak current limitin g for constant output power * built-in synchronized slope compensation * otp,olp,ovp, lno-ov, brownout and v dd clamp for higher security * fixed switch frequency 65khz * gate output voltage clamped at 16v * low start-up current * cycle-by-cycle current limiting * under voltage lockout (uvlo) * few external components required ? ordering information ordering number package packing UC3800g-s08-r sop-8 tape reel
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 2 of 10 www.unisonic.com.tw qw-r103-083.a ? marking ? pin configuration ? pin description pin no. pin name pin type description 1 gate o totem-pole gate driver output for power mosfet. 2 v dd p supply voltage 3 cs i current sense input. 4 lno i this pin is connected to the line input via two resistors to achieve line voltage over protect function and brownout 5 fb i the pwm duty cycle is determined by voltage level into this pin and the current-sense signal at cs pin. 6 gnd p ground. 7 nc 8 hv i connected to the line input or bulk capacitor via resistor for setup.
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 3 of 10 www.unisonic.com.tw qw-r103-083.a ? block diagram hv vdd hv start internal supply en uvlo ovp clamp en r s q ovp delay delay r q s logic green mode driver osc soft start ocp leb slope compensation pwm comparator burst mode + - + - vth_olp 2r r olp comparator + - vth_lno gate cs fb lno gnd
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 4 of 10 www.unisonic.com.tw qw-r103-083.a ? absolute maximum ratings (t a =25c, v dd =16v, unless otherwise specified) parameter symbol ratings unit supply voltage v dd 30 v input voltage to fb pin v fb -0.3~6 v input voltage to cs pin v sense -0.3~6 v junction temperature t j +150 ? c operating temperature t opr -40~+125 c storage temperature t stg -50~+150 ? c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? operating range parameter symbol ratings unit supply voltage v dd 9~24 v ? thermal data parameter symbol ratings unit junction to ambient ja 150 c/w
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 5 of 10 www.unisonic.com.tw qw-r103-083.a ? electrical characteristics (t a =25c, v dd =16v unless otherwise specified) parameter symbol test conditions min typ max unit supply section supply current from hv pin i hv hv=100v 0.25 ma start up current i str v dd = v dd(on) -0.1v 2 15 a ic operating current i op1 v fb =3.5v 0.8 1.8 ma v dd zener clamp voltage v dd(clamp) i dd =20ma 31 33 35 v under-voltage lockout section start threshold voltage v dd(on) 12 13 14 v min. operating voltage v dd(off) 6 7 8 v hysteresis v dd(hy) 6 v control section v fb open loop voltage level v fb-open 5.0 5.4 v pwm input gain a vcs ? v fb / ? v cs 3 v/v the fb threshold enter burst mode v fb(in) v sense =0 1.5 v the fb threshold exit burst mode v fb(out) v sense =0 1.8 v the fb threshold enter green mode v fb(end) v sense =0 2.9 v normal v fb =3.5v, hopping rang 60 65 70 khz switch frequency power-saving f sw before enter burst mode 19 22 25 khz duty cycle d max v fb =3.5v, v sense =0 70 78 85 % frequency hopping f j(sw) -4 +4 % frequency vdd stability f dv v dd =12v~20v 5 % frequency temperature stability f dt t=-25~85c 5 % protection section vcc over voltage protection threshold v ovp v fb =3.5v 26 27 28 v fb pin over load protection threshold v olp 4.3 v over load protection delay-time t delay 80 88 96 ms soft start time t ss 2.5 ms otp level t otp 145 c current limiting section peak current flat threshold voltage v cs-f v fb =3.5v, duty 60% 0.85 0.95 1.05 v peak current valley threshold voltage v cs-v v fb =4.2v, duty=0% 0.55 0.65 0.75 v lead edge blanking time t leb 350 ns driver output section output voltage low state v ol v dd =16v,i o =-20ma 0.8 v output voltage high state v oh v dd =16v,i o = 20ma 11 v output clamp voltage v_clamping 16 v output voltage rise time t r c l =1.0nf 100 ns output voltage fall time t f c l =1.0nf 60 ns lno section threshold voltage for lno v th_lno 1.05 v threshold voltage for bno v th_bno 0.3 v
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 6 of 10 www.unisonic.com.tw qw-r103-083.a ? operation description the utc UC3800 devices integrate many useful designs into one controller for low-power switch-mode power supplies. the following descriptions highlig ht some of the f eatures of the utc UC3800 series. hv start-up utc UC3800 integrated hv start circuit, and provide about 1m a current to charge vdd pin during power on state from hv pin. when vdd cap vo ltage is higher than uv lo (off), the charge current is switched off. at this moment, the vdd capacitor provides current to utc UC3800 until the auxiliary winding of the main transformer starts to provide the operation current. power-saving mode operation the proprietary power-saving mode function provides linearly decreasing the switching frequency under light-load conditions for higher efficiency. the feedback volt age, which is sampled from the voltage feedback loop, is taken as the reference. once the feedback voltage dropped below the thresh old voltage, the switching frequency starts to decrease. this power-savin g mode function dramatically reduce s power consumption under light-load conditions. the 22khz minimum frequency control also elim inates the audio noise at any loading conditions. at zero load condition, the magnitude of power loss is in proportion to the number of switching events within a fixed period of time. reducing switching events leads to the reduction on the power loss and thus conserves the energy. the utc UC3800 enter burst mode at standby condition to mi nimize the switching loss and reduces the standby power consumption. power supplies using the utc UC3800 can easily meet even t he strictest regulations regarding standby power consumption. switch frequency set the maximum switch frequency is fixed to 65khz. switch frequency is modulated by output power p out during ic operating. at no load or light load cond ition, most of the power dissipation in a switching mode power supply is from switching loss on the mosfet transistor, the core loss of the transformer and the loss on the snubber circuit. the magnitude of power loss is in proportion to the number of sw itching events within a fixed period of time. so lower switch frequency at lower load, which more and more improve ic?s efficiency at light load. at from no load to light load condition, the ic will operate at from burst m ode to reducing frequency mode. the relation curve between f sw and p out /p out (max) as followed fig.1. fig.1 the relation curve between f sw and relative output power p out / p out (max)
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 7 of 10 www.unisonic.com.tw qw-r103-083.a ? operation description (cont.) frequency hopping for emi improvement the frequency hopping is implemented in the ic; there are two oscillators built-in the ic. the first oscillator is to set the normal switching frequency; the switching frequency is modulated with a period signal generated by the 2nd oscillator. the relation between the first oscillator and th e 2nd oscillator as followed fig.2. so the tone energy is evenly spread out, the spread spectrum minimizes the conduction band emi and therefor e eases the system design in meeting stringent emi requirement. fig.2 frequency hopping built-in slope compensation built-in slope compensation circuit greatly improv es the close loop stabilit y at ccm and prevents the sub-harmonic oscillation. leading-edge blanking each time the power mosfet is switched on, a turn-on sp ike will inevitably occur at t he sense-resistor. to avoid premature termination of the switching pulse, a 350ns leading-edge blanking time is built in. conventional rc filtering can therefore be omitted. during this blanking period, the curr ent-limit comparator is disabled and it cannot switch off the gate driver. constant output power limit when the sense voltage, across the sense resistor r s , reaches the threshold volta ge, around 0.95v, the output gate drive will be turned off after a small propagation delay t d . this propagation delay will introduce an additional current proportional to t d v in /lp. since the propagation delay is nearly co nstant regardless of the input line voltage v in . higher input line voltage will result in a larger additional current and hence the output power limit is also higher than that under low input line vo ltage. to compensate this variation for wi de ac input range, the threshold voltage is adjusted by the v in current. since v in pin is connected to the rectified i nput line voltage through a resistor r vin , a higher line voltage will generate higher v in current into the v in pin. the threshold volt age is decreased if the v in current is increased. smaller threshold voltage, forces the output gate drive to termi nate earlier, thus reduce the total pwm turn-on time and make the output power equal to that of low line input. this proprietary internal compensation ensures a constant output power limit for wide ac input voltage from 90vac to 264vac. under voltage lockout (uvlo) the turn-on and turn-off thresholds of the utc UC3800 are fixed internally at v thd(on) /v dd(min) during start-up, the hold-up capacitor must be charged to v thd(on) through the start-up resi stor, so that the utc UC3800 will be enabled. the hold-up capacitor will continue to supply v dd until power can be delivered from the auxiliary winding of the main transformer. v dd must not drop below v dd(min) during this start-up process. this uvlo hysteresis window ensures that hold-up capacitor will be adequate to supply v dd during start-up. gate output the utc UC3800 output stage is a fast totem pole gate driver. cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. a good tradeoff is ac hieved through dead time control. the low idle loss and good emi system design is easier to ac hieve with this dedicated control scheme. an internal 16v clamp is added for mosfet gate protection at higher than expected v dd input.
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 8 of 10 www.unisonic.com.tw qw-r103-083.a ? operation description (cont.) protection controls the ic takes on more protection functions such as ovp, olp and otp etc. in case of those failure modes for continual blanking time, the driver is shut down . driver is reset after failure is eliminated. ovp the ovp will shut down the switchin g of the power mosfet whenever v dd >v ovp . the ovp event as followed fig.3. fig.3 ovp case fig.4 olp case olp olp will shut down driver when v fb > v olp for continual time. the olp event as followed fig.4. lno-ovp and bno lno will shut down driver when lno> v th _ lno or lnoUC3800 , and increasing the power mos gate resistance is advised.
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 9 of 10 www.unisonic.com.tw qw-r103-083.a ? refrence circuit (12v/1.5a) sense vdd gate gnd fb lno u1 7 1 2 6 r6 r9 r5 r7 q1 1 3 22 c8 3 c1 + c2 c3 r3 d2 10 9 8 5 7 t1 d5 r10 c9 c10 + 1, 2 3, 4 211 2 1 2 zd1 + c11 l1 v o gnd r15 r14 c12 r16 u2 3 1 2 r12 2 1 3 4 u3 d3 2 1 c4 + bd1 2 1 4 12 l2 cx1 f1 l n cy1 8 3 r2 r1 c7 r8 r4 d4 2 1 r13 c5 c13 r9-1 hv nc 4 5 bom reference component reference component bd1 bd 1a/600v l2 20mh 6*8mm cx1 (optional) nc q1 4n60 cy1 (optional) yc 220p/400v (y1) r1,r2 r 1m ? 1206 c2 ec 22 f/400v 105c r3 r 30k ? 1206 c1 ec 10 f/400v 105c r4 (optional) r 20 ? 1w c3 cc 0.01 f/1000v r5 r 0 ? 1206 c4 ec 3.3 f/50v r6 r 100 ? 1206 c5,c13 (optional) cc 104p/25v 0805 r7 r 1.1 ? 1w c7 (optional) cc 102p/25v 1206 r8 r 10k ? 1206 c8 cc 102p/25v 1206 r9/r9-1 r 12k ? 0805 c9 cc 222p/100v 1206 r10 r 51 ? 0.5w c10 ec 470u/16v 105c r12 r 510 ? 0805 c11 ec 220u/16v 105c r13 r 2k ? 0805 c12 cc 222p/16v 0805 r14 r 0 ? 0805 c14 nc r15 r 43k ? 0805 d2 diode fr107 r16 r 12k ? 0805 d3 diode fr102 r17 r 120k ? 0805 d4 (optional) t1 ef-20 d5 diode sb360 u1 ic UC3800 f1 r1 ? /0.5w u2 tl431 l1 10 h 6mm u3 pc817
UC3800 preliminary linear integrated circuit unisonic technologies co., ltd 10 of 10 www.unisonic.com.tw qw-r103-083.a utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
|
